1. Field of the Invention
The present invention relates to a technique to avoid unintended rewriting of data or reduce the possibility thereof, due to repeated readouts of data from a nonvolatile memory.
2. Description of the Background Art
NAND flash memories, among nonvolatile memories, are heavily used for SD memory cards or the like for the purpose of achieving high integration, reduction in manufacturing cost and easy writing for users by simplifying circuit configurations.
In recent, NAND flash memories are adopted for game machines or the like. When the NAND flash memories are used for game machines, there occurs no write operation but only consecutive read operations. In other words, NAND flash memories have been increasingly adopted as ROMs.
Since specific programs are repeatedly read out in the game machines or the like in most cases, however, it begins to be noticed that the programs could be unintendedly rewritten. Such a phenomenon is termed “read disturb phenomenon”, and the mechanism of this phenomenon will be briefly discussed below.
FIG. 11 is a schematic diagram showing a NAND flash memory. The NAND flash memory is constituted of a bit line 41 and word lines 42, 43 and 44 which are arranged in a lattice manner, memory cells 52 and 53, a selection transistor 54 and the like.
In a case where binary data (“0” or “1”) stored in the memory cell 52 is read out, the memory cell 52 is a selected cell and the memory cell 53 is an unselected cell. First, the selection transistor 54 specifies the bit line 41 to which the selected cell 52 belongs. Next, a low gate voltage (V(Low)=0V) is applied to the word line 42 to which the selected cell 52 belongs. Then, a high gate voltage (V(High) of approximately 5V) is applied to the word line 43 to which the unselected cell 53 belongs.
At that time, since the unselected cell 53 is in a very weak writing condition, electrons are trapped in a floating gate of the unselected cell 53 and accumulated therein. In other words, when binary data stored in the selected cell 52 is repeatedly read out, there is a possibility that a threshold voltage of the unselected cell 53 might be shifted and binary data stored in the unselected cell 53 might be unintendedly rewritten, being changed from “1” to “0”.
Even if the binary data stored in the unselected cell 53 is unintendedly rewritten, however, when data are collectively erased before new data are written, it is possible to recover the function of the unselected cell 53. But, if there occurs no write operation and only consecutive read operations, it is impossible to recover the function of the unselected cell 53.
US Patent Application Publication No. 2005/0210184 discloses means for avoiding the above-discussed “read disturb phenomenon” by controlling the inside of a memory cell. This disclosed method, however, can be applied to a memory having a specific cell configuration but can not be applied to any other cell configuration. In other words, by this method, it is impossible to avoid the “read disturb phenomenon” without depending on cell configurations of memories.
Japanese Patent Application Laid-Open No. 8-129510 (“JP No. 8-129510”) discloses means for carrying out error detection. However, a method disclosed in JP No. 8-129510 is a method of carrying out error detection at an address which is used for readout (“readout address”), and is not applicable to error detection at an address which is not used for readout (“non-readout address”). That is, even if an error occurs at a certain address, occurrence of the error can not be detected until the certain address where the error has occurred is accessed for readout. Thus, the method disclosed in JP No. 8-129510 can not avoid a “read disturb phenomenon”.